Phase locked loops (PLLs) are control systems that are common in high performance microprocessors and transceivers. A phase locked loop generates an output signal with a phase related to the phase of a highly accurate input signal (reference signal). A PLL is typically used to ensure that the clock frequencies of signal inputs of various registers and flip-flops match the frequency generated by an oscillator. Without a PLL, clock skew may become a problem resulting in the registers and flip-flops not receiving the clock at the same time.
Traditional analogue PLLs utilise a voltage controlled oscillator (VCO) to provide an oscillating waveform with a variable frequency. The output of the VCO is compared to a reference input signal by a phase detector, which compares the phase of the input and output signals and adjusts the oscillator to keep the phases matched. This acts as a feedback loop.
The frequency of the output may be varied by introducing a divider that allows the output frequency to be a multiplied copy of the lower reference frequency, which is usually insensitive to process voltage and temperature variations. However, this provides the constraint that the oscillator frequency must be equal to an integer multiple of the reference frequency. Such analogue circuits are called integer-N frequency synthesisers.
This limitation may be overcome by introducing a modulator or dither to divide the value of the divider to achieve fractional divide values. The resulting variations are smoothed by the PLL using a loop filter. Such analogue PLL's are called fractional-N frequency synthesisers.
However issues with noise become apparent through the use of such analogue electronic components in modern digital electronics. For example, one problem with implementing a traditional analogue PLL is the difficulty in integrating this on a digital chip. Additionally, analogue PLLs are susceptible to noise and process variations.
Whilst digital components can be utilised in place of the analogue components, for example by using a digitally controlled oscillator, a counter, phase difference module and by controlling the components with digital command logic, such components tend to have a higher power requirements. This results in higher power consumption for the chip and therefore the chip being unsuitable for low power applications such as radio transceivers.
One route to reduce the power consumption is to duty cycle the digital PLL. Such an approach is described in WO2010/113108. Although this provides a reduced power consumption, this duty cycled all digital phase locked loop (DC-ADPLL) circuit operates as an integer-N frequency synthesiser.
There therefore exists a need to provide a duty cycled digital fractional-N frequency synthesiser. Accordingly, it is an object of the present invention to address one or more of the above mentioned problems relating to digital frequency synthesisers.
Summary
In accordance with a first aspect of the invention there is provided a frequency synthesiser circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal: a delay module configured to delay an input reference signal to generate a delayed reference signal; a duty cycle module configured to modulate the oscillator enable signal based on a period of the input reference signal and the delayed reference signal such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer.
By providing a non-integer fractional ratio between the output signal generated by the digitally controlled oscillator and the input reference signal, a fractional-N frequency synthesiser can be provided. This allows a narrower range or channel spacing to be provided by the frequency synthesiser circuit because the frequency of the output signal can be more flexibly adjusted compared to an integer-N frequency synthesiser. Additionally, by modulating or duty cycling the oscillator enable signal, power consumption can be reduced. This control is achieved by providing control of the delay added to the reference signal which is then used to duty cycle the frequency synthesiser.
The signals described herein are typically digital signals and can be considered to comprise low and high levels and rising and falling edges.
The digitally controlled oscillator optionally comprises a ring oscillator and a digital to analogue converter configured to receive the (filtered) error signal and to provide a voltage signal to the ring oscillator that determines the frequency of the output signal and therefore also the delay of the ring oscillator stages. Ring oscillators are quicker to start up than LC oscillators and are generally suited due to the requirement that the output signal be stable at the start of each pulse.
The ring oscillator generally comprises a plurality of delay stages arranged in a closed loop (Nring). This allows the output frequency to be controllable by varying the input voltages applied to the delay stages.
In embodiments, the delay module comprises a delay module feedback loop configured to regulate the delay of the delayed reference signal compared to the input reference signal.
Providing a delay module feedback loop allows for a feedback mechanism between the output or wanted frequency and the delayed reference signal supplied by the delay module. Once the delay is settled, the delay of the delay module is stable and provides a ratio with the oscillator enable signal and with the output signal. In this manner, changes to the delay applied to the input reference signal are applied to the oscillator enable signal, which in turn alters the output signal and can be fed back into the delay module feedback loop.
An oscillator feedback loop is optionally connected to the digitally controlled oscillator, the oscillator feedback loop configured to regulate the output frequency. The feedback loop may be configured to count the number of rising and falling edges of the output signal to generate a feedback count value and to compare the feedback count value with a frequency control word (FCW). The difference between the feedback count value and FCW is an error signal. The frequency control word is used to program the wanted output frequency of the digitally controlled oscillator. More particularly, the feedback loop typically comprises a counter module and a phase difference module, the counter module being configured to count cycles of the output signal from the digital controlled oscillator while the digital controlled oscillator is configured to provide an output phase signal to the phase difference module, the phase difference module configured to compare the value of number of cycles counted by the counter module and the frequency control word, and to provide the error signal.
The feedback loop may comprise a first feedback loop configured to provide coarse control of the output frequency of the digital controlled oscillator and a second feedback loop configured to provide fine control of the output frequency of the digital controlled oscillator. The use of a second feedback loop for fine frequency control allows for fine tuning to align the last rising edge of the DCO output with the reference clock rising edge, reducing the total error and improving accuracy.
The delay module feedback loop may also be a signal generator circuit provided with feedback mechanism and components configured in a similar manner to the oscillator feedback loop described above.
The duty cycle module may comprise a timing unit to generate the oscillator enable signal based on the input reference signal and the delayed reference signal. The oscillator enable signal can be provided by a timing unit. The timing unit can accept the input reference signal and the delayed reference signal. For example, the oscillator enable signal may be the sum of the period of the input reference signal and the delay indicated by the delayed reference signal. The timing unit acts to modulate the oscillator enable signal based on the input reference signal and the delayed reference signal.
A timing unit alone tends to be non-high speed and cannot apply an offset or delay. Accordingly, it can be necessary to generate a separate reference delayed signal. Furthermore, the timing unit may be optimised to minimise uncontrollable delays, for example by tailoring the topography or by calibrating the unit. Furthermore, any error potentially introduced by the timing unit can be minimised by ensuring that an XOR is as accurate as possible.
The delay applied to the input reference signal by the delay module can be varied to generate a range of output frequencies of the output signal such that each output frequency within the range differs by a selected fractional channel spacing. By varying the delay, the timing of the oscillator enable signal is altered. This in turn alters the output signal and may also alter the output frequency. By controlling the delay, and therefore the timing of the oscillator enable signal, the output signal and output frequency can also be controlled. Because the delay applied to the input reference signal is incremental, an incremental range of output frequencies of the output signal can be generated.
In embodiments, a divider may be configured to reduce the frequency at which the delay module operates. Typically, the frequency at which the delay module operates is dependent upon a delay module input signal and a frequency control word of the delay module. The divider reduces the frequency of operation of the delay module by an integer value. In this case, the frequency of operation of the delay module can be an integer division of the output frequency. This frequency is based on a delay module input signal. The delay module input signal may be the output frequency. The delay module input signal may be the oscillator enable signal.
The divider can be configured to alter the frequency of adelay module input signal to be an integer division of the frequency of the output signal. For example, the divider can act to provide the frequency of the delay module input signal at a frequency ¼ that of the output signal. This exemplary configuration of the divider allows for a lower power consumption of the delay module and therefore of the circuit.
The divider may be a module configured to receive the output signal and to generate a delay module input signal input to the delay module.
The divider can act to provide the frequency of the delay module input signal at an integer division of the frequency of the output signal.
By introducing a divider, the operating frequency of the delay module can be an integer division of the output frequency.
The delay module may comprise a time delay oscillator, driven by an oscillator control voltage, and be configured to delay the delay module input signal by an amount based on the number of stages of the time delay oscillator.
The time delay oscillator may be configured to generate the delay based upon the input reference signal and on the delay module input signal. Additionally the delay module feedback loop can be connected between an output and an input of the signal generator. This ensures that the delay generated is stable.
In embodiments, the delay module comprises a multiplexer with a selectable channel input; and a copy time delay oscillator configured to be controlled by said oscillator control voltage and operable to delay the input reference signal to generate the delayed reference signal.
For example, by providing a multiplexer with a channel input, this provides versatility and allows a varying amount of delay to be chosen by selecting a channel that corresponds to the delay or channel spacing required.
By utilising a divider and/or a multiplexer and copy time delay oscillator, the delay of the delayed reference signal can correspond to a frequency channel spacing selected by modifying either one or both of the channel input and/or the integer.
In embodiments, the time delay oscillator is a ring oscillator and the stages are ring stages. The ring oscillator can be driven by a ring control voltage and operable to or configured to generate a signal based on the delay module input signal or the divided delay module input signal.
As noted above, ring oscillators are quicker to start up than LC oscillators and are suited due to the requirement that the output signal be stable at the start of each pulse. The ring oscillator generally comprises a plurality of ring stages arranged in a closed loop. This allows the frequency of the delay module input signal to be controllable by varying the input voltages applied to the ring stages or by selecting the number of ring oscillator ring stages. The overall control voltage required to generate the delay module frequency can then be determined.
Furthermore, in embodiments, the copy time delay oscillator is a copy ring oscillator with a number of copy ring stages, wherein the number of active ring stages is controlled by the channel input of the multiplexer.
Providing a copy ring oscillator couples the ring oscillator of the delay module and the timing unit. The ring control voltage for the copy ring oscillator is shared with the ring control voltage of the ring oscillator of the delay module. This effectively couples the ring oscillator of the delay module and the copy ring oscillator. As such, each delay stage of the copy ring oscillator provides a controllable amount of delay.
The number of ring stages of the copy ring oscillator can be selected to provide the needed delay for different fractional channels. The value of the channel input can determine the number of active copy ring stages. In this instance, the amount of delay applied to the input reference signal depends on the number of active copy ring stages.
In embodiments, the copy ring oscillator contains 2×Nring delay stages, where Nring is the number of ring stages of the ring oscillator. In embodiments, the copy ring oscillator is an exact copy of the ring oscillator. This allows for matching of the delay introduced to the reference signal by the copy ring oscillator. The copy ring oscillator can be controlled by the same control voltage as the ring oscillator.
The delay to the input reference signal is generated by a providing a signal having a frequency an integer division of that of the output signal as an input to the ring oscillator. Because the copy ring oscillator is driven by the same ring control voltage as the ring oscillator, by selecting the number of copy ring stages of the copy ring oscillator the input reference signal will be delayed by a fractional portion of the delay of the ring oscillator. In this manner, the delay of the input reference signal can be varied in steps corresponding to the output channel spacing.
The time delay oscillator can be considered to be a feedback system. As a delay is selected by the channel input on the multiplexer, the delay provided to the input reference signal by the copy time delay oscillator varies. This in turn is fed to the timing unit, which varies the frequency of the output signal. Because the delay module input signal is based on a feedback mechanism involving the output signal, the frequency of the time delay oscillator also changes. Due to the coupling between the time delay oscillator and the copy time delay oscillator, variations between the two outputs become reduced until the outputs synchronise or lock in.
Accordingly, the value of the channel input can determine the number of active copy ring stages, wherein the timing of the oscillator enable signal depends on the number of active copy ring stages. In this manner, variation in the delay of the input reference signal provided by the copy ring stages can correspond to a frequency channel spacing selected by the channel input and/or the integer. This allows the channel spacing between the frequencies of the output signal for different channel inputs to be controlled by controlling the selected channel and/or the value of the integer.
In the above described embodiments, the delay module may be considered to be a phase locked loop. In one embodiment, the delay module is a phase locked loop. In particular, an all digital phase locked loop. The phase locked loop may comprise: a frequency feedback loop connected between an output and an input of the ring oscillator, the frequency feedback loop configured to regulate the frequency of the delay module.
In an alternative embodiment, the time delay oscillator may be a delay line. In this embodiment, the stages are delay stages. The delay line may be configured to be driven by a line control voltage and configured to generate a delay in the input reference signal, wherein the delay module is configured to regulate the delay module input signal by altering the line control voltage. The delay module may comprise a delay line feedback loop connected between an output and an input of a delay line, the delay line feedback loop configured to regulate the delay module input signal.
Furthermore, the copy time delay oscillator may comprise a copy delay line with a number of copy delay stages, wherein the number of active delay stages is controlled by the channel input of the multiplexer. The copy delay line may be configured to be driven by said line control voltage and operable to generate the delay. Providing a copy delay line couples the delay module and the timing unit. The line control voltage for the copy delay line is shared with the line control voltage of the delay line of the delay module. This effectively couples the delay line of the delay module and the copy delay line, resulting in a fractional channel spacing.
The number of copy delay line stages of the copy delay line can be selected to provide the required phase shift or delay of the input reference signal. The value of the channel input can determine the number of active copy delay lines. In this instance, the delay applied to the input reference signal depends on the number of active copy delay lines.
Accordingly, the value of the channel input can determine the number of active copy delay line stages, wherein the delay depends on the number of active copy delay line stages. In this manner, variation in the delay between the copy delay line stages can correspond to a frequency channel spacing selected by the channel input and/or the integer. This allows the channel spacing between the frequencies of the output signal for different channel inputs to be controlled by controlling the selected channel and/or the value of the integer.
As noted above, in embodiments, altering the number of copy delay stages of the copy delay line may alter the phase of the delayed reference signal relative to the input reference signal. In this example, the spacing between the copy delay stages corresponds to a frequency or delay channel spacing selected by the channel input. When a delay line is employed, the delay module may be considered to be a delay locked loop
In such embodiments containing a delay line, the delay module can be considered to be a delay locked loop.
As noted above, the oscillator enable signal can be duty cycled for the period of the input reference signal plus the time introduced by the delay. Applying the delay to the period of the reference input signal allows the circuit to lock to a fractional channel frequency of the frequency of the input reference signal.
In accordance with a second aspect of the invention there is provided a radio receiver comprising a frequency synthesiser circuit according to the first aspect of the invention. The various optional features of the first aspect may also be applied to the radio receiver of the second aspect.